vhdl – i keep on getting these erros when i try to program the FPGA on the MachX03 series development board. Can someone please help me fix these?

This is my code;

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    
    entity CC2510_prac3 is
        port(clkin: in std_logic;
            reset: in std_logic;
            SW3: in std_logic;
            SW2: in std_logic;
            SW1: in std_logic;
            com: out std_logic;
            D2_out: out std_logic_vector(6 downto 0);
            D1_out: out std_logic_vector(6 downto 0);
            D0_out: out std_logic_vector(6 downto 0);
            DP1_out: out std_logic;
            DP2_out: out std_logic;
            LED_out: out std_logic_vector(7 downto 0));
        
    --  define the pin connections
        attribute loc:string;
        attribute loc of clkin: signal is "C8";
        attribute loc of D0_out: signal is "R13,T14,T12,R11,T11,M11,N10";
        attribute loc of D1_out: signal is "R10,P10,T10,R9,T9,N9,M8";
        attribute loc of D2_out: signal is "M6,L8,T8,P8,R7,R8,T7";
        attribute loc of com: signal is "P7";
        attribute loc of reset: signal is "D2";--SW4
        attribute loc of SW3: signal is "E2";--SW3
        attribute loc of SW2: signal is "F2";--SW2
        attribute loc of SW1: signal is "G2";--SW1
        attribute loc of DP1_out: signal is "P9";
        attribute loc of DP2_out: signal is "P11";
        attribute loc of LED_out: signal is "F3,D3,G3,C2,F5,E3,B1,C1";
        end;
    
    architecture seq_arch of CC2510_prac3 is
    
        type state_type is (S0, S1, S2, S3, C, E1, EE1, E2, E);
        signal state, next_state : state_type;
        signal clkreg : std_logic_vector(31 downto 0);
        signal c_clk: std_logic;
        signal dig2: std_logic_vector(6 downto 0):="1111111";
        signal dig1: std_logic_vector(6 downto 0):="1111111";
        signal dig0: std_logic_vector(6 downto 0):="1111111";
        signal DP1: std_logic:='1';
        signal DP2: std_logic:='1';
        signal oscpin: std_logic;
        signal errcount: integer range 0 to 4:=0;
        signal displayerr: std_logic:='0';
        
    begin
        
        clk1:process(clkin)
            begin
             if (clkin'event and clkin = '1') then          
                clkreg <= clkreg+X"00000001";
            end if;
            
            c_clk <= clkreg(19);
            oscpin <= clkreg(15);
        end process clk1;
        
        lcdmod:process(oscpin)
            begin
             if (oscpin='1') then
                D2_out<=dig2;
                D1_out<=dig1;
                D0_out<=dig0;
                DP1_out<=DP1;
                DP2_out<=DP2;
             else
                D2_out<= not dig2;
                D1_out<= not dig1;
                D0_out<= not dig0;
                DP1_out<=not DP1;
                DP2_out<=not DP2;           
             end if;
                com<=oscpin;
        end process;
             
        seq: process (reset,c_clk) is 
           begin 
            if reset="0" then
                state <= S0;
            elsif rising_edge(c_clk) then
                state <= next_state;
            end if;
           end process seq;
    
        comb: process (SW1,SW2,SW3,state) is
            begin 
                dig2 <= "1111111";          
                dig1 <= "1111111";
                dig0 <= "1111111";
                DP1 <= '1';
                DP2 <= '1';
            
            case state is
            when S0 => 
            if SW1 = '0' then
                next_state <= S1;
            elsif (SW2 = '0' or SW3 = '0') then
               next_state <= E1;--was E1
            else
                next_state <= S0;
                LED_out<="00000000";
            end if;
            when S1 => 
            if SW1 = '1' then
                next_state <= S2;
            else
                next_state <= S1;
            end if;
            when S2 => 
            if SW2 = '0' then
                next_state <= S3;
            elsif (SW1 = '0' or SW3 ='0') then
               next_state <= E2;
            else
                next_state <= S2;
            end if;
            when S3 =>
            if SW2 = '1' then
                next_state <= S4;
            elseif (SW1 = '0' or SW3 ='0') then
               next_state <= S3;
            end if;
                    when S4 => 
            if SW2 = '0' then
                next_state <= S5;
            else
                next_state <= S4;
            end if;
                    when S5 => 
            if SW2 = '1' then
                next_state <= S6;
            elseif (SW1 = '0' or SW2 ='0') then
                next_state <= S5;
            end if;
                    when S6 => 
            if SW3 = '0' then
                next_state <= c;
            else
                next_state <= S6;
            end if;
                     when c => 
            if SW4 = '0' then
                next_state <=S0 ;
            else
                next_state <= c;
            end if;
    
            when C =>
                dig0 <= "0110001";
                next_state <= C;
                LED_out<="01010101";
            
                    when E1 =>
            if (SW2 = '1' or SW3 = '1' or SW3 = '0') then
                next_state <= EE1;
            else
                next_state <= E1;
            end if;
            when EE1 =>
            if (SW1 = '0' and SW2 = '0' and SW3 = '0') then
                next_state <= E2;
            else
                next_state <= EE1;
            end if;
              when E2 =>
            if (SW1 = '1' and SW3 = '1' and SW3 = '1') then
                next_state <= EE2;
            else
                next_state <= E2;
            end if;
            when EE2 =>
            if (SW1 = '0' or SW2 = '0' or SW3 = '0') then
                next_state <= E3;
            else
                next_state <= EE2;
            end if;
                    when E3 =>
            if (SW1 = '1' or SW2 = '1' or SW3 = '1') then
                next_state <= EE3;
            else
                next_state <= E3;
            end if;
            when EE3 =>
            if (SW1 = '0' or SW2 = '0' or SW3 = '0') then
                next_state <= E;
            else
                next_state <= EE3;
            end if;
                     when E => 
            if SW4 = '0' then
                next_state <=S0 ;
            else
                next_state <= E;
            end if;
            when E =>
                dig0 <= "0110000";
                LED_out<="10101010";
                next_state <= E;            
           end case;
         end process comb;
    end architecture seq_arch;

These erros keep coming up when i try to run it and I have no idea how to fix it: WARNING – CG296 :”C:UsersjosnaDocumentspractical2.vhd”:69:8:69:14|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.

WARNING – CG290 :”C:UsersjosnaDocumentspractical2.vhd”:76:12:76:14|Referenced variable dp2 is not in sensitivity list.

WARNING – CG290 :”C:UsersjosnaDocumentspractical2.vhd”:75:12:75:14|Referenced variable dp1 is not in sensitivity list.

WARNING – CG290 :”C:UsersjosnaDocumentspractical2.vhd”:74:11:74:14|Referenced variable dig0 is not in sensitivity list.

WARNING – CG290 :”C:UsersjosnaDocumentspractical2.vhd”:73:11:73:14|Referenced variable dig1 is not in sensitivity list.

WARNING – CG290 :”C:UsersjosnaDocumentspractical2.vhd”:72:11:72:14|Referenced variable dig2 is not in sensitivity list.

WARNING – CD638 :”C:UsersjosnaDocumentspractical2.vhd”:46:8:46:11|Signal dig2 is undriven. Either assign the signal a value or remove the signal declaration.

WARNING – CD638 :”C:UsersjosnaDocumentspractical2.vhd”:49:8:49:10|Signal dp1 is undriven. Either assign the signal a value or remove the signal declaration.

WARNING – CD638 :”C:UsersjosnaDocumentspractical2.vhd”:50:8:50:10|Signal dp2 is undriven. Either assign the signal a value or remove the signal declaration.

WARNING – CL240 :”C:UsersjosnaDocumentspractical2.vhd”:13:2:13:4|Signal LED is floating; A simulation mismatch is possible.

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